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Extra resources for Digital Fundamentals Tenth Edition Instructor Solution Manual
See Figure 3-23. FIGURE 3-23 Section 3-7 Fixed-Function Logic 27. The power dissipation of CMOS increases with frequency. 28. 4 V (max) @ VCC = 2 V, tPHL = tPLH = 75 ns; @ VCC = 6 V, tPHL = tPLH = 13 ns 30 Chapter 3 29. See Figure 3-24. FIGURE 3-24 30. Gate A can be operated at the highest frequency because it has shorter propagation delay times than Gate B. 31. PD = VCCIC = (5 V)(4 mA) = 20 mW 32. ICCH = 4 mA; PD = (5 V)(4 mA) = 20 mW Section 3-8 Troubleshooting 33. (a) (b) (c) (d) (e) (f) NAND gate OK AND gate faulty NAND gate faulty NOR gate OK XOR gate faulty XOR gate OK 34.
PD = VCCIC = (5 V)(4 mA) = 20 mW 32. ICCH = 4 mA; PD = (5 V)(4 mA) = 20 mW Section 3-8 Troubleshooting 33. (a) (b) (c) (d) (e) (f) NAND gate OK AND gate faulty NAND gate faulty NOR gate OK XOR gate faulty XOR gate OK 34. (a) (b) (c) (d) NAND gate faulty. Input A open. NOR gate faulty. Input B shorted to ground. NAND gate OK XOR gate faulty. Input A open. 35. (a) The gate does not respond to pulses on either input when the other input is HIGH. It is unlikely that both inputs are open. The most probable fault is that the output is stuck in the LOW state (shorted to ground, perhaps) although it could be open.
G = H 3 H 2 H 1 H 0 + H 3 H 2 H1 H 0 + H 3 H 2 H 1 H 0 + H 3 H 2 H 1 H 0 + H 3 H 2 H 1 H 0 FIGURE 4-33 58 Chapter 4 60. The invalid code detector must disable the display when any numerical input (0-9) occurs. A HIGH enables the display and a LOW disables it. A circuit that detects the numeric codes and produces a LOW is shown in Figure 4-34. FIGURE 4-34 Multisim Troubleshooting Practice 61. Input A inverter output open. 62. Input A of segment e OR gate open. 63. Segment b OR gate output open. 59 CHAPTER 5 COMBINATIONAL LOGIC ANALYSIS Section 5-1 Basic Combinational Logic Circuits 1.